The address decode circuit is designed to set CE at low level when the address output by the CPU is the EPROM address.
The EPROM should be designed to operate only when the address output by the CPU is the EPROM address (from H'000000 to H'07FFFF) and operation is enabled only when the CE pin of the EPROM is set at low level. Next, let's develop an address decode circuit. The smallest addresses are from H'000000 to H'07FFFF. Since the CPU memory space is 16Mbytes and the EPROM capacity is 512kbytes, the CPU memory space is divided into 32 equal parts. Generally, a memory is assigned to one of the spaces obtained by equally dividing the CPU memory space by the memory capacity. The internal ROM is assumed to be disabled here. In internal ROM disable mode, the HN27C4001G must be connected between H'000000 and H'01FFFF. In internal ROM enable mode, the internal ROM addresses are from H'000000 to H'01FFFF. Since the reset vector is between H'000000 and H'00003, a ROM must be connected to starting from the H'000000 address if only one ROM is connected. What should be determined first is to which addresses the memory is to be connected.Īs described in "Exception Handling", a program operating based on resetting and the reset vector must be located in a ROM.
HM628512BI-8 for SRAM (access time: 85ns)įirst, let's consider how to connect a CPU to a memory using an 8-bit data bus.
Memory: HN27C4001G-10 for EPROM (access time: 100ns) RD, HWR and CS0 to CS7 are used as control signals Internal ROM disabled (internal ROM is not used but an EPROM is connected externally) The following conditions are assumed here for connecting a CPU to a memory: 13.7 Connecting CPU to Memory (Connecting EPROM Using 8-bit Data Bus)
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